Design/Verify FGPAs For Acacia's Product and Evaluation platform; Write Python routines for Test Development and Automation; Contribute to FPGA Emulation of ASIC Blocks; Contribute to our custom ASIC RTL code

5+ years of FPGA design and verification experience; Experience in Verilog RTL coding and synthesis for FPGAs; Experience with Python and Linux; Experience designing interfaces with Processors, SPI & I2C devices, MDIO, high speed SERDES, etc.; Experience in Xilinx® design tool chain for design, place, and route (ISE®, Vivado® suite)

C/C++ and experience coding with embedded MCUs; Experience in designs and timing closure with multiple clock domains; Experience work in labs and experience with test equipment to help with board level and FPGA bring up; Experience with analog components (OpAmps, DACs/ADCs, etc.); Experience implementing digital control loops and DSP functions; Experience with Xilinx FPGA families such as Ultrascale+; Experience with Synopsys VCS simulation and Synplify® synthesis tools for FPGAs; Expertise in creating FPGA implementations from ASIC RTL code; Expertise in digital design of standard cell ASICs; Experience presenting technical information to technical and non-technical audiences.