Hardware Design & Verification Engineer – ASIC/FPGA
Mainz Brady Group
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El Segundo, CA
Mid-Senior level
Over 200 applicants applicants
About This Role

We're seeking a talented Hardware Design & Verification Engineer to join a high-impact team supporting complex ASIC/FPGA projects. You’ll work directly with engineering teams to deploy advanced functional verification solutions, helping customers maximize productivity and influence product direction.

Roles & Responsibilities

Support RTL verification and simulation flows using SystemVerilog/UVM; Deliver technical training and collaborate with R&D on tool enhancements; Troubleshoot functional verification issues and contribute to documentation; Engage directly with customers to optimize RTL power and formal verification usage; Influence product development based on real-world customer feedback

Required Skills

Solid experience in ASIC/FPGA RTL design using VHDL, Verilog, or SystemVerilog; Proficiency with C/C++ and Object-Oriented Programming in a verification context; Hands-on knowledge of UVM, constrained-random testing, and simulation tools; Strong communication and customer-facing skills

Education Requirements

BS in EE/CE required; MS preferred

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