Vertex Elite is currently seeking a qualified FPGA Design & Verification Engineer to join their team. If you or someone you know is interested, please feel free to reach out for more details or share your updated resume. Work Authorization : USC or Any valid USA work authorization(At this moment, we are not providing any sponsorships). Job Type : W2 with Vertex Elite LLC. Location : Mountain View, California, United States.
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Strong understanding of FPGA design principles, digital design fundamentals, and FPGA architectures. Proficiency in SystemVerilog for RTL design and testbench development. Hands-on experience with the UVM (Universal Verification Methodology) for building scalable and reusable verification environments. Familiarity with industry-standard verification tools, such as QuestaSim, Synopsys VCS, or similar simulators. Ability to debug and analyze complex design and verification issues.
Experience with simulation, synthesis, and timing analysis tools is a plus.
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